1. Field of the Invention
This invention relates to an improvement of an electronic controller having a microprocessor using MRAM (Magnetic Random Access Memory) as a nonvolatile memory able to easily perform reading and writing operations at high speed as a program memory and a data memory.
2. Background Art
In the electronic controller using the microprocessor, it is considered to use MRAM as a nonvolatile memory able to easily perform the reading and writing operations at high speed instead of a former memory construction in which a nonvolatile memory of a mask ROM memory or a flash memory, etc. is set to a program memory, and a battery-backed-up RAM memory is set to a data memory for arithmetic processing.
However, there is a high possibility that stored data are easily changed by a noise error operation, etc. although it is convenient to easily perform the reading and writing operations at high speed. Accordingly, prudent dealing is required.
For example, in accordance with JP-A-2003-104137 (Patent Document 1), a memory area of MRAM is divided into a RAM area and a ROM area, and a write inhibiting means with respect to the ROM area is arranged. When a maintenance tool is also connected with respect to the RAM area, the controller is constructed to perform writing inhibition by commands from a control terminal so as not to delete stored data in error. Thus, the controller is considered such that writing and erasion are not carelessly performed.
Further, in accordance with JP-A-2003-115197 (Patent Document 2), MRAM for obtaining error correction decoding data by using error correction coding data stored to the solid memory device (MRAM) is disclosed. Read-out data are restored when a code error is generated in the range of a limited bit number. In addition, in accordance with JP-A-2005-208958 (Patent Document 3) as a technique relating to this invention, a program area of a memory is divided into suitable areas, and is partitioned into plural data blocks. Further, sum check data of stored program data and an error correction code are stored to each data block together. At a starting time of the microcomputer, a sum check of the program data is performed. When no sum check is conformed, a data restoring program is started and an abnormal portion of the program data is found. Further, normal data of a pertinent portion are calculated and the program data are restored.
In accordance with the above Patent Document 1, there is an important point in a writing inhibition function for executing no erroneous writing operation. The correction of a generated error, the detection of an error unable to be corrected, and an abnormality processing countermeasure are not referred. Accordingly, there is a defect in that no controller of high safety can be obtained by merely performing the writing inhibition. Further, in accordance with the above Patent Document 2, there is a limit in a correctable error bit number, and no countermeasure processing of an error of a bit number exceeding this correctable error bit number is referred.
For example, when a correction code of three bits is added to data of four bits, the error can be corrected within the range of one bit. However, when a code error of two bits is generated, a problem exists in that this error cannot be corrected. In this state, it is dangerous to operate the microprocessor.
However, there are defects in that a correction code bit length becomes large so as to make the error correction of many bits, and the memory is large-sized and becomes expensive. Further, in accordance with the above Patent Document 3, even when a code error of many bits is generated within one data, the original correct data can be arithmetically calculated and presumed. However, when code errors are simultaneously scattered and generated in plural data, a problem exists in that no code errors can be recovered.